LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--input comes from the PC and PC+4 from the adder
entity regfetch is
  port ( 
    CLK							     :		 in	std_logic;
    nReset         :   in std_logic;
    ifen           :   in std_logic;
    
    
    fInstruction   :   in std_logic_vector(31 downto 0);
    fPC4           :   in std_logic_vector(31 downto 0);
    
    
    dInstruction   :  out std_logic_vector(31 downto 0);
    dPC4           :  out std_logic_vector(31 downto 0)
  );
end regfetch;

architecture arch of regfetch is
  signal q0, n0  : std_logic_vector (31 downto 0);  --Instruction
  signal q1, n1  : std_logic_vector (31 downto 0);  --PC4
  
begin
  
  proc : process(CLK,nReset)
  begin
    if (nReset = '0')  then
      q0 <= x"00000000";
      q1 <= x"00000000";

    elsif rising_edge(CLK) then
      q0 <= n0;
      q1 <= n1;

    end if;
  end process proc;

  n0 <= fInstruction when ifen = '1' else
        q0 when ifen = '0' else
        x"00000000";
  n1 <= fPC4 when ifen = '1' else
        q1 when ifen = '0' else
        x"00000000";


  dInstruction            <= q0;
  dPC4                    <= q1;

  
     
end arch;